4 bit Binary Decrementer

Basic Theory:

The binary decrementer decreases the value stored in a register by ‘1’. For this, we can simply add ‘1’ to the each bit of the existing value stored in a register. This is basically the concept of two's complement used for subtraction of '1' from given data. It is made by cascading ‘n’ full adders for ‘n’ number of bits i.e. the storage capacity of the register to be decremented. Hence, a 4-bit binary decrementer requires 4 cascaded full adder circuits. As stated above we add '1111' to 4 bit data in order to subtract '1' from it. 

Circuit Diagram:

Observed Values:

Following set of values were obtained in observation.
1.      0011 => 0010
2.      1010 => 1001
3.      1101 => 1100
4.      0010 => 0001
5.      0000 =>1111

Reference:

Mano, M. (n.d), Register Transfer and Micro-operations: Arithmetic Circuit, Computer System Architecture (3^rd Edition), pp. 106-108