**Basic Theory:**

The
binary decrementer decreases the value stored in a register by ‘1’. For this, we can simply add ‘1’ to the each bit of the existing value stored in a register. This is basically the concept of two's complement used for subtraction of '1' from given data. It
is made by cascading ‘n’ full adders for ‘n’ number of bits i.e. the storage capacity
of the register to be decremented. Hence, a 4-bit binary decrementer requires 4
cascaded full adder circuits. As stated above we add '1111' to 4 bit data in order to subtract '1' from it.

**Circuit Diagram:**

**Observed Values:**

Following
set of values were obtained in observation.

1. 0011 => 0010

2. 1010 => 1001

3. 1101 => 1100

4. 0010 => 0001

5. 0000 =>1111

1. 0011 => 0010

2. 1010 => 1001

3. 1101 => 1100

4. 0010 => 0001

5. 0000 =>1111

**Reference:**

Mano,
M. (n.d), Register Transfer and Micro-operations: Arithmetic Circuit,

*Computer System Architecture (3*, pp. 106-108^{rd}Edition)
Thanx

ReplyDeleteCould u plz provide combinational logic unit description of n bit decrement or..

ReplyDeleteAnd trace the same for 1111😊

This works for 1111; you just need to discard the carry out. Also, you can cascade as many units to implement your n-bit decrementer. I do not see any problem here :)

Delete"a 4-bit binary decrementer requires 4 cascaded half adder circuits"

ReplyDelete4 Half Adders or 4 Full Adders?

Why the diagram explain using full adders not half adders?

what if i want it using half adders?

This implementation uses the concept of two's complement. It is basically an adder which will add "1111" to make the end result look like a decremented one (Carry out us discarded). You can try using half-adders but the logic will be different.

Deletecan u make it using half Adders?

ReplyDelete