Thursday, 21 March 2013

4 bit Binary Incrementer


Basic Theory:

The binary incrementer increases the value stored in a register by ‘1’. For this, it simply adds ‘1’ to the existing value stored in a register. It is made by cascading ‘n’ half adders for ‘n’ number of bits i.e. the storage capacity of the register to be incremented. Hence, a 4-bit binary incrementer requires 4 cascaded half adder circuits.

Circuit Diagram:


Observed Values:

Following set of values were obtained in observation.
1.      0011 => 0100
2.      1010 => 1011
3.      1101 => 1110
4.      0010 => 0011
5.      1111 => 0000; Cout = 1

Reference:
Gamezero.com (n.d.), Designing and Building our 4-bit Addition Engine, Processor Design, Accessed: February 15, 2013, Retrieved from: http://www.gamezero.com/team-0/articles/math_magic/micro/stage1.html

4 comments:

  1. Please can you tell me that how can we design a 4 bit binary incrementer using full adder?

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    Replies
    1. Using a full adder is not necessary, as you can see it works perfectly with half-adders. But it is interesting to think about such an implementation. Full adder has two outputs, and a binary incrementer has just one. So, how will they be cascaded to produce a single output is the main question.

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    2. F.A consists of 3 inputs, A, B, carry_in .just give input to one of the two inputs(A or B) and let other number be zero. the carry_out part should be connected to the carry_in of the next F.A. give logic 1 to the carry_in of first half adder and you are good to go.

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  2. What are the A_ and I_ supposed to be? I know the far right line is the last output, and I am assuming that the logic high is just always 1.

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